The present invention pertains to a data processing system and, more particularly, to an apparatus and method for partitioning a signal interface into multiple groups, each controlled by a separate clock.
Known data processing systems typically include one or more processing components that have a defined signal interface and protocol to facilitate communication with other components. In most cases, the interface is controlled by a single, fixed synchronous clock. A single clock keeps the design simple, but limits the ability to isolate timing problems, recover from errors, manage power and otherwise run certain interfaces at different frequencies than other interfaces.
The use of multiple clocks in data processing systems is known. For example, U.S. Pat. No. 5,790,609 to Swoboda discloses a data processing system featuring multiple clock inputs delivered to a single multiplexer. When it is desirable to run the data processing system at a slower rate, for example to conserve power, then instructions are generated causing the multiplexer to change its clock output from a faster clock input to a slower clock input. Unfortunately, providing only a single clock output at different selectable frequencies does not address the need to provide certain input/output signals within a data processing system at one frequency or skew and other input/output signals at a different frequency or skew.
One aspect of the present invention is a data processing system comprising a plurality of processing components, each connected to at least one other of the processing components. The system also includes a plurality of clock sources, each providing a clock signal, and a plurality of controllers associated with each of the processing components. In addition, the system includes a plurality of clock select registers, each providing a clock select signal, and a plurality of multiplexers, each connected to the plurality of clock sources, to two or more of the plurality of controllers, and to one of the clock select registers. Each of the multiplexers provides as an output to the two or more of the plurality of controllers one of the clock signals in response to a clock select signal provided by the one clock select register.
Another aspect of the present invention is a method of providing clock signals in a data processing system having a plurality of processing components and a plurality of controllers associated with the processing components. As the first step in the method, a plurality of different clock signals is provided. Next, one of the plurality of clock signals is selected for each of the plurality of controllers. Finally, the selected ones of the plurality of clock signals is provided to the plurality of controllers in parallel.